Saravanan, S.

• Identification of DNA Elements Involved in Somaclonal Variants of Rauvolfia Serpentina (L.) Arising from Indirect Organogenesis as Evaluated by ISSR Analysis

Abstract Views :394  |  PDF Views:162

Authors

S. Saravanan ¹, R. Sarvesan ², M. S. Vinod ³

Affiliations
1 Post-graduate & Research Dept. of Plant biology and Biotechnology, Pachaiyappa’s College, Chennai-600030, IN
2 Post-graduate & Research Dept. of Plant biology and Biotechnology, Presidency College, Chennai-600005, IN
3 M.S.Swaminathan Research Foundation, Chennai-600 113, IN

Source

Indian Journal of Science and Technology, Vol 4, No 10 (2011), Pagination: 1241-1245

Abstract

Rauvolfia serpentina an endangered medicinal plant was chosen for in vitro propagation using modified MS medium. Genetic fidelity study of the regenerated plants were analysed with 18 ISSR markers. A total of 159 monomorphic bands were obtained; one ISSR marker HB-12 showed a polymorphic band among the callus regenerants. The specific polymorphic fragment was then gel eluted, cloned and sequenced.

Keywords

Rauvolfia serpentina, ISSR, Somaclonal variation, Medicinal plant, India

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References

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• Countermeasure against Side Channel Power Attacks in Cryptography Devices

Abstract Views :227  |  PDF Views:0

Authors

K. P. Sridhar ¹, S. Saravanan ², R. Vijay Sai ²

Affiliations
1 VLSI Design, School of Computing, SASTRA University, Thanjavur, Tamil Nadu- 613401, IN
2 School of Computing, SASTRA University, Thanjavur, Tamil Nadu- 613401, IN

Source

Indian Journal of Science and Technology, Vol 7, No S4 (2014), Pagination: 15-20

Abstract

Power attack is the most powerful side channel attacks in cryptography chip during VLSI (Very Large Scale Integration) testing. Hackers attack the target devices by means of power through finding the correlations between the power spikes for different input generated on Cathode Ray Oscilloscope (CRO). To overcome such a great issues we proposed the novel techniques for cryptography devices which perform their crypto functions without an external power source. Energy required to do the cryptographic operation is provided by Embedded Capacitance Power Supply (ECPS) method, which is integrated with the VLSI device. Group of capacitors are connected to form the power supply, which act as the temporary battery of the cryptographic chip. The power spikes for this crypto operation not visible by the CRO. Hence it is complicate for attackers to hack the crypto system. The proposed method is modelled through Hardware Description Language (HDL) Verilog-AMS using Switch Level Modelling and result is verified by simulation wave form generated.

Keywords

Cryptography Chip, Embedded Capacitance Power Supply, Side Channel Attack, Vlsi Testing

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• Rectifying Various Scan-based Attacks on Secure IC'S

Abstract Views :198  |  PDF Views:0

Authors

C. Ramya ¹, S. Saravanan ²

Affiliations
1 VLSI Design, SASTRA University, Thanjavur-613401, Tamil Nadu, IN
2 School of Computing, SASTRA University, Thanjavur-613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 13 (2015), Pagination: 

Abstract

Designing of confidential ICs must satisfy many design rules in order to rectify the various attacks and to protect the secret data. Based on the concept of withholding information, on-chip comparisons for actual and expected response have already been proposed. From the security point of view, few limitations of existing method limit the security level. Some countermeasures have been proposed in order to secure the scan technique and on-chip comparison. In this paper, an additional inverter is introduced within the scan chain architecture. The introduction of flipped scan chain increases the switching of scan output and increases the complexity to retrieve the secret data. On comparing with Traditional scan chain, proposed method results in only negligible area overhead with high security level. This result shows that possible trials will be more than to hack the data. The proposed method can be applied for all scan testing.

Keywords

Flipped Scan Chain, On-Chip Comparison, Scan Chain

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• Design and Analysis of Low Power Memory Built in Self Test Architecture for SoC based Design

Abstract Views :258  |  PDF Views:0

Authors

Sowmithra Vennelakanti ¹, S. Saravanan ²

Affiliations
1 VLSI Design, SASTRA University, Thanjavur, IN
2 School of Computing, SASTRA University, Thanjavur, IN

Source

Indian Journal of Science and Technology, Vol 8, No 14 (2015), Pagination: 

Abstract

This paper targets on the low power design of Memory Built In Self Test (MBIST) architecture for System on Chip (SoC) based design. Proposed address generator is developed with the blend of gray code counter and modulo counter. Bit reversing technique is adopted in this paper to generate the last pattern of gray code counter. In this work a refined architecture of MBIST is also constructed by embedding a low power address generator in it. Efficient employment of the proposed address generator in MBIST has cut-down the power consumption of BIST architecture compared to the traditional BIST. Reduction of about 6% of switching activity has been observed with novel MBIST architecture.

Keywords

Gray Code, Low-Power, MBIST, Modulo Counter, MUT

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• Low Power Estimation on Test Compression Technique for SoC based Design

Abstract Views :182  |  PDF Views:0

Authors

P. Raja Gopal ¹, S. Saravanan ²

Affiliations
1 VLSI Design, SASTRA University, Thanjavur, 613401, IN
2 School of Computing, SASTRA University, Thanjavur, 613401, IN

Source

Indian Journal of Science and Technology, Vol 8, No 14 (2015), Pagination: 

Abstract

Test power dissipation is one of the major challenging task in System on Chip (SoC). The objective of the paper is to reduce the power consumption during testing in VLSI testing field. This paper analyzes the test power consumption for the test data to get the low power consumption by using switching activity. The Low Power Transition – X filling (LPT-X) method is proposed to reduce the transition switching where unknown bits were filled. Weighted Transition Metric (WTM) method used to estimate low test power. This paper approach achieves reduction of average power consumption by LPT-X filling method. Using ISCAS89 benchmark circuits the experimental results were conducted and achieves 83 percent of reduced average test power.

Keywords

Low Power Transition (LPT), Switching Activity, System on Chip (SoC), Test Power, Weighted Transition Metric (WTM), X-Filling

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• Improved CAPTCHA based Authentication for E-mail ID

Abstract Views :182  |  PDF Views:0

Authors

K. Naveen ¹, S. Saravanan ¹, M. Lavanya ¹, V. Vaithayanathan ²

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
2 SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 35 (2015), Pagination: 

Abstract

This article aims to present the importance of authentication for E-mail ID through improved CAPTCHA based method.The structure of the CAPTCHA has to be reorganized to suit the user requirements to facilitate the authentication for E-mail ID. CAPTCHA is achieved by rearrangement of alphabets randomly on the buttons and it is very easy to frustrate by simple keyloggers. The motive of improving E-mail authentication is done by incorporating two factor visual authentication mechanisms. It is targeted to CAPTCHA based human interaction with sophisticated user friendly protocol. All the intermediate interaction is visualized by the user with better CAPTCHA code. It provides only one time (or) one session valid authentication through color grid rating method. This two layer authentication promises more secure in accessing any secure information based portal.

Keywords

Authentication, CAPTCHA, E-mail, Hacker Attack, Keyloggers

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• An Enhanced Load Balancing Scheduling Approach on Private Clouds

Abstract Views :181  |  PDF Views:0

Authors

M. Lavanya ¹, Aarthi Ravi ², Ajay Aditya ², Rukmani Samyuktha ², V. Vaithiyanathan ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
2 SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 35 (2015), Pagination: 

Abstract

This paper aims to bring enhanced load balancing scheduling on private cloud computing. As cloud computing has become a developing and emerging area, the need for a cloud becomes mandatory in working areas. The advantage of technology in their own data centers to evolve a private cloud. Due to the presence of private cloud and to fulfill its unique characteristics and special requirements, it becomes a challenging task to optimally schedule virtual machine instances requests onto nodes to compute when there are multiple tasks to satisfy. In this paper, we discuss about load balancing, which is to schedule task among various end users. The scheduling algorithm used is Round Robin algorithm. This algorithm reduces the response time and improves the processing speed. According to this algorithm the nodes are allocated to the virtual machines along with their corresponding task to a particular node in a cyclic fashion. Each node in the cloud is scheduled equally with the task until all the tasks in the global queue all allocated.

Keywords

Cloud Computing, Load Balancing, Private Cloud, Round Robin Algorithm, Scheduling

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• Secure Aware Communication using Novel End To End (ETE) Cipher Algorithm

Abstract Views :167  |  PDF Views:0

Authors

M. Lavanya ¹, G. Aishwarya ², S. Keerthana ², V. Vaithiyanathan ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
2 Information and Communication Technology, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 35 (2015), Pagination: 

Abstract

This article aims to bring a novel method in cipher algorithm for secure aware communication. This paper proposes a unique scheme and ensures higher security during encryption and decryption process. The Key (ki) is generated for every Plain text pi. Plain text and key are converted to their equivalent ASCII values, by which the scrambled Cipher text (ci) is generated by implementing some of the concepts of the substitution techniques. During Decryption, the corresponding (ki) are used to recover the Plain text pi. It makes sure the need to send the full length key along with the cipher text for decryption process. The suggested method assures the greater security during transmission. There is a practical hindrance in guessing the Number of rounds (N) and the number of bits n shifted, by Cryptanalyst. This method will be more suitable for analyzing the discover key (ki) values from attempting Brute Force technique.

Keywords

Ciper Algorithms, Cryptanalyst, Decryption, Encryption, Secure Communication

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• A Constraint-based Decentralized Task Routing Approach to Large-Scale Scheduling in Cloud Environment

Abstract Views :179  |  PDF Views:0

Authors

M. Lavanya ¹, T. N. Janani ², S. Sushmita ², M. Sunandha ², V. Vaithiyanathan ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
2 Information and Communication Technology, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 35 (2015), Pagination: 

Abstract

This article mainly focused on cloud scheduling with constraint based decentralized task routing. The job of scheduling tasks across various nodes in a hierarchical network scenario is an exigent problem. The concept of decentralized distribution scheme proposed in base paper is time-consuming since it has to compute the availability function for each and every node. In this paper we proposed a CBDA (Constraint Based Decentralized Algorithm) which offers the expediency of being quick and “Make-span minimization policy” is implemented to reduce the completion time of the currently executing nodes. In our presumption, the submission nodes are semi centralized and it can store the availability information of the nodes or routers within its area. This paper considers the allotment of the tasks to the execution nodes which are unoccupied by other tasks. The dynamic allotment of the tasks to the nodes in the tree based approach is the major criteria for selecting the desired node. This paper proposes a trade-off between fully centralized model and the decentralized model by implementing a new constraint based decentralization scheme which saves time consumption and enhances efficiency of task scheduling.

Keywords

Cloud Computing, Constraint based Method Scheduling, Decentralized Router, Dynamic Task

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• Implementation of a Novel Data Scrambling based Security Measure in Memories for VLSI Circuits

Abstract Views :163  |  PDF Views:0

Authors

R. Vijay Sai ¹, S. Saravanan ¹, V. Anandkumar ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 35 (2015), Pagination: 

Abstract

This article shows the importance of security in memory for VLSI circuits based on data scrambling and overcome attacks. Security information stored in memory is very valuable. The model should not be prone to intruder attacks. The proposed method provides scrambling of information by data scrambling vectors. Instead of using some extra table for scrambling the data in cache memories, the data is divided into two halves and scrambled within to overcome extra hardware and memory requirement. This method is implemented in Verilog HDL using Model Sim which has improvement in area and memory requirement. This method is more suitable for value added applications such as smart cards and bio metric applications.

Keywords

Cache Read and Write Operations, Scrambling Vectors, Security in Memory

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• Modified Privacy Protection in Personalized Web Search

Abstract Views :172  |  PDF Views:0

Authors

T. Prasannakumar ¹, K. Thangaprakash ¹, S. Saravanan ², M. Lavanya ², V. Vaithayanathan ³

Affiliations
1 B. Tech Information Technology, School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
2 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN
3 Research, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 36 (2015), Pagination: 

Abstract

This proposed work aims to show the importance of personalized web search with improved privacy protection. To protect user profile based on Personalized Web Search (PWS), we need to consider few major issues during web site search processing. It is possible to improve efficient search based method with the personalized usage method of the accessing new user profile and prevent the privacy contents, which exists in the user profile method to adopt the risk privacy under control. User privacy can be safe without compromising the web search if personalized search quality. User Profile Search Engine (UPSE) is typically offline with all queries received from a same user. This article provides an inexpensive method for the user clientto conform whether to personalize a web search query in UPSE. This can avoid the unnecessary experience of the profile. Expected results can be evident that UPSE can achieve better quality based search results. So this proposed method is more applicable for personalized web portal.

Keywords

Greedy Algorithms, Personalized Web Search, Privacy Preserving Personalized, User Profile Search Engine

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• Multiple Scan Base Partitioning Technique to Increase the Throughput in VLSI Testing

Abstract Views :199  |  PDF Views:0

Authors

P. Ramalakshmi ¹, S. Saravanan ²

Affiliations
1 School of Computing, SASTRA University, Thirumalaisamudram, Thanjavur – 613401, Tamil Nadu, IN
2 School of Computing, Information Technology, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 29 (2016), Pagination: 

Abstract

Among any testing methods, scan testing is very significant for both in built and external schemes. The performance of the system should get maintained so the throughput plays major role. This paper tells about the retaining data which is hold technique and the jump process is attached to improve the throughput in VLSI testing. In order to achieve better performance the throughput is achieved by transferring the data per time and this gets increased constantly. The data in the partitions shifted sequentially when scan condition is on and when it is off the data may get corrupted so the system invalidate the testing process, the loss may get increase. In-order to solve the problem the data should get retained when the scan condition is not activated and to this process the jump technique is connected. The jump process connects to the output port when the condition is off. When compared to the first stage hold process this multiple partitions is beneficial. The implemented technique helps for the priority data, data rate and also to increase the throughput value approximately 85% to 87% as the clock frequency get reduced in the testing side. The area is reduced by 23.01% with the help of ISCAS benchmark circuit S5378when compared to the first stage hold technique where the benchmark helps to test the system.

Keywords

Hold Technique, Jump Technique, Multiple Scan Base Partition, Throughput, VLSI Testing.

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• Efficient Test Sequence Generator for Area Optimization in LFSR Reseeding

Abstract Views :163  |  PDF Views:0

Authors

D. S. Nivetha Joice ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 29 (2016), Pagination: 

Abstract

In this paper, a new concept of test pattern generator is used with Seed Initialization Method (SIM) for area optimization in LFSR reseeding. LFSR Reseeding is the method which is mainly used in logic BIST. Some of the reseeding mechanism needs some sort of memory to store all seeds. But this issue is overcome by present method. By this method, the proposed test pattern generator employs the output response of the CUT to the LFSR as the controlling signal to transform the LFSR state. It contains a net providing cell and LFSR with reversal logic to conform that there is no storage of seeds. When compared to previous methods, by using this approach (SIM), the test sequence that will have been given to LFSR is much reducing. The empirical outcome on ISCAS circuits shows that the conferred seed initialization method has brought reduced area overhead.

Keywords

BIST, LFSR Reseeding, Seed Initialization Method, Test Sequence Generator (TSG).

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• Cell Stability and Power Reduction using Dynamic Isolated Read Static Random Access Memory

Abstract Views :210  |  PDF Views:0

Authors

M. S. Vandhana ¹, R. Vijay Sai ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur -613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 29 (2016), Pagination: 

Abstract

The channel scaling attains the overflow current at the transistor, which impacts on power indulgence. In order to attain reduced power and delay, the devices are assumed to decrease its size. Then transistors size can also be changed. In this paper the unique dynamic isolated read SRAM has been projected for dropping the total power. By linking, the cell with 6T and NC SRAM in numerous features, high constancy and decreased power is achieved by the curvature N (noise) method, which is done when the system is in active mode. The values are calculated with the voltage of 1.8 which reduces 90% of power than the 6T, and 18% of power is reduced than the 8T SRAM cell, and 30% of leakage current is reduced as compared to 6T cell. Thus when related to the existing SRAM, the cell consumes less power and without any distortion the cell stores the data. Also the constancy of the cell is improved when compared with the other cell. The waveform result shows that the cell attains enhanced stability and reduction in overflow using the cadence virtuoso technology of 180 nm.

Keywords

Curvature-noise, Stability, Static Current Noise Margin, Static Voltage Noise Margin, Write Trip Point.

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• Improving the Reliability of Cache Memories using Identical Tag Bits

Abstract Views :155  |  PDF Views:0

Authors

S. Manju Bharathi ¹, R. Vijay Sai ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 29 (2016), Pagination: 

Abstract

Cache memories are revealed to transitory error in tag bits and some of the efforts have been taken to decrease their susceptibility. In the advanced mechanisms of cache memories are most applicable components, because the soft errors are protected. The identical tag bit data is used to regain from the error in the tag bits. In this paper, to improve error protection capacity of the tag bits in caches, power efficient cache design is proposed by using Superlative Standard Techniques (SST) architecture to achieve power. To utilize the identical tag bits for transitory error protection, the proposed scheme is discussed by selecting the energy superlative standard techniques that decrease unwanted interior activities by reducing the dynamic switching power. In experimental method, results show that our proposed multilevel cache architecture sustains a performance of achieving dynamic power and reduces the power consumption up to 85% when applied to energy optimal technique.

Keywords

Cache Memories, Identical Tag Information, Superlative Standard Techniques (SST), Tag Bits, Transitory Error.

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• Compression of Data using Shifted Frequency Directed Reference Coding and MISR

Abstract Views :129  |  PDF Views:0

Authors

N. Padma Priya ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur - 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 29 (2016), Pagination: 

Abstract

In modern technology BIST become pervasive where scan chain plays a major role. An efficient low power BIST method is proposed which occurs in testing. The test set acquires sequence of preprocessed approach inclusive of X-bit 2-D reordering and cube matrix is sequentially distributed. In this paper compression ratio is achieved using MISR. The introduction of MISR and X-masking technique will reduce the compression Ratio. To minimise the repitation of bits MISR plays a vital role. Compression is done by the run length coding and the high compression is achived by the first and second matrix response. MT flling is a method for the replacement technique.CR is calculated using the output values used. The ratio of input bits used to the existing input values which shows the compression ratio. This proposed technique is compared with bench mark circuits s5378, s9234 and s13207 to analyze the area and compression ratio.

Keywords

Hamming Distance, Multiple Input Scan Register (MISR), X-Masking, Scan Chain.

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• Low Power Testing based on MOS Design Modified Flip-Flop

Abstract Views :137  |  PDF Views:0

Authors

Anjali Chava ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamilnadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 29 (2016), Pagination: 

Abstract

Flip-flops are basically data storage elements which can be used for storage of state. However, most non-volatile memory forms have limitations which make them unsuitable for primary storage. One of the disadvantages of existing flip-flop normal flip-flop based circuits and its computing is relatively high write energy to build up normal flip-flop based circuits. There is a need to reduce the consumption of power and to write energy of flip-flop. Hence, we propose a design of low power normal flip-flop using modified CMOS technology. CMOS technology provides less noise ration during design. The proposed flip-flop design is based on MOS technology. Data store and restore operations can be performed. And in the proposed design performs in retaining data when electrical power fails or is turned off with low power consumption.

Keywords

CMOS Design, D Flip-Flop, Low Power.

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• Construction of Rural Roads using C&D Waste Materials

Abstract Views :198  |  PDF Views:0

Authors

S. Saravanan ¹, C. Venkatasubramanian ², D. Muthu ², K. Ramakrishnan ²

Affiliations
1 School of Civil Engineering, Sastra University, Thanjavur - 613401, Tamil Nadu, IN
2 Faculty, School of Civil Engineering, Sastra University, Thanjavur – 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 27 (2016), Pagination: 

Abstract

Objective: Soil is often weak in sustaining heavier loads. In this study, investigations are made to determine the use of C&D (Construction & Demolition) waste materials in geotechnical applications such as formation and strength improvement of rural roads, and to evaluate the effects of powdered waste bricks & prolonged stored cement in the formation of rural roads. Analysis: The results obtained are made towards the effectiveness and usability of reinforcement as a replacement for pavement works used in rural road execution works as a cost effective approach. Findings: By addition of C&D waste materials in the sub-base layer of the road structure, the conventional laterite layer of rural road formation is further strengthened, quantity of utilization of laterite is reduced and thus leads to cost reduction in road laying. Applications/ Improvements: Due to the improvement of the strength in the sub-base layer subsequently the water bound macadam layer which is laid on the top of laterite layer will be stabilized further, thus increasing the life of the rural roads to a certain extent.

Keywords

CBR Test, Construction & Demolition Waste, Rural Roads, Soil Stabilization, Soil Tests, Soil Replacement, Soil Tests.

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• Business Configuration of Windchill PDMLink 10.0 For MR Manufacturing Company

Abstract Views :160  |  PDF Views:0

Authors

R. Jeyaganeshan ¹, K. Sivakumar ², S. Saravanan ¹

Affiliations
1 Department of Production Engineering, PSG College of Technology, Coimbatore – 641004, Tamil Nadu, IN
2 Department of Mechanical Engineering, Bharath University, Chennai – 600073, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 8, No 31 (2015), Pagination: 

Abstract

One of the leading manufacturers of educational products such as interactive whiteboards is currently using PTC suite of PLM products (PDMLink 10.0). This project deals with business configuration of the system to enable capabilities that address functional business requirements and desired features. Out of-the-box business configurations like the default numbering scheme, lifecycle templates, versioning series, object initialization rules, attributes and other related configurations of the existing Windchill environment are already packaged in the Windchill PDMLink 10.0 environment. There are certain features such as custom roles, custom lifecycle states, custom versioning series, soft types, workflow, lifecycle, organization creation, object initialization rules, access control rules for libraries and products which are specific to an organization and are recommended to be defined at the organization level. This can be achieved by deploying configured files into this Windchill PDMLink 10.0 system using Load files, import function and other manual settings.

Keywords

PDMLink 10.0, PLM, PTC, Lifecycle, Workflow

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• A Review on Security in Cache Memories

Abstract Views :160  |  PDF Views:0

Authors

R. Vijay Sai ¹, S. Saravanan ¹

Affiliations
1 School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 48 (2016), Pagination: 

Abstract

Objectives: Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations. The objective of this review is to analyze various attacks targeting cache memory and suggest remedial measures to thwart such attacks and assure cache memory security. Methods/Statistical Analysis: Information stored in cache memory can be recovered whenever required. This data is in danger of being hacked by the intruder. Statistical analysis show that attacks such as side channel attacks, timing attacks and power based attacks are adopted to challenge information security in caches. Findings: Discussed solutions involve in the design of secured cryptographic based algorithms, secure aware cache mapping and low power cache design by employing techniques such as code convertors, nested XOR operations, extended Hamming codes and multi-bit clustered ECC. Application/Improvements: Improving and authenticating cache memory security will result in numerous applications involving smart cards and bio-metric applications where secrecy of data is of extreme importance.

Keywords

Cache Memory, Power Based Attacks, Side Channel Attack, Timing Attacks.

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• Modified Block Based Technique for Efficient Test Data Compression

Abstract Views :151  |  PDF Views:0

Authors

S. Saravanan ¹, S. Sharmila ²

Affiliations
1 School of Computing, SASTRA UNIVERSITY, Tirumalaisamudram, Thanjavur - 613401, Tamilnadu, IN
2 Deaprtment of Master in Technology, VLSI Design, SASTRA University, Tirumalaisamudram,Thanjavur - 613402, Tamilnadu, IN

Source

Indian Journal of Science and Technology, Vol 9, No 48 (2016), Pagination: 

Abstract

Test data compression is one of the major challenging tasks in VLSI. This paper targets on Test Data compression by using block based method without any variation in the system performance. Test data sets are separated into five kinds of blocks like whole zeros, whole ones, min zero/min one, max ones and complement blocks. The blocks will be read based on the presence of 0s and 1s. The analysis made in the ISCAS89 benchmark circuit shows that the proposed method is more efficient and more flexible and produces a good compression ratio when compared to the existing methods.

Keywords

Data Compression, Code Based Compression, Min Zero - Min One Test Pattern, Test Patterns.

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